1. Field of the Invention
The present invention relates to a semiconductor structure and a method for forming the same. More particularly, the present invention relates to a semiconductor with an HfxMoyNz layer serving as the electrode.
2. Description of the Prior Art
Complementary metal-oxide-semiconductors (CMOS) are a major class of integrated circuits. According to the polarity of the CMOS channel, the CMOS can be divided into P-type and N-Type, i.e. PMOS and NMOS. CMOS technology is used in chips such as microprocessors, microcontrollers, static RAM, and other digital logic circuits. In addition, a CMOS consumes power only during its switching on or off time. Therefore power is saved and heat generation is reduced during the operation of the CMOS.
Functionally speaking, PMOS and NMOS each have different threshold voltages, which are determined by the difference of the work function of the gate and the channel material.
When using the metal gate in the CMOS fabrication, the Fermi level of the metal gate is preferably at the midpoint of the silicon. In this way, the threshold voltage of the PMOS and CMOS can be easily adjusted to meet the requirement. In general, the threshold voltage PMOS and CMOS are adjusted by utilizing two different metals as the gate materials.
Because two layers of different metals are required to form the gate material, the two layers are formed separately. For example: a first gate electrode material layer is entirely formed on a substrate, then a selective etching is performed based on a well defined patterned hard mask, a second gate electrode material layer fills the space defined by the selective etching, and finally the surfaces of the first gate electrode material layer and the second gate electrode material layer are planarized to complete the fabrication.
Another example of fabricating the gate with two layers of different metals is described herein: a sacrificial layer is entirely formed on a substrate top face, later, the sacrificial layer is selectively removed to allow a first gate electrode material to fill in gaps defined by the removal of the sacrificial layer, and then the sacrificial layer is completely removed to allow a second gate electrode material layer to fill in gaps from the removal of the sacrificial layer to complete the fabrication.
No matter which method is used, a selective etching must be performed to form different metal layers for respectively deciding the threshold voltages of the PMOS and NMOS. It is clear that the concept of first forming the first gate electrode material layer followed by an etching process to form the second gate electrode is both complex and troublesome and does not meet the demand of simplicity pursued by the industry. Therefore, a novel material is needed to form gates with different work function.
Capacitors are widely used in the semiconductor industry, especially as data-storage elements in DRAMs. A capacitor includes a top electrode, a bottom electrode and a dielectric layer. The top electrode and bottom electrode can be made of tungsten (W), aluminum (Al), titanium (Ti), and ruthenium (Ru), etc. In order to scale down the element size, the dielectric layer is usually made of a high-k material such as hafnium silicon oxynitride (HfSiON), or titanium oxides (TiO2). Because of the material heterogeneity, a bad affinity exists between the dielectric layer and the electrode. Therefore, a peeling problem will occur between the dielectric layer and the electrode during the fabricating process. Accordingly, a novel material is in need to solve the material heterogeneity between the dielectric layer and the electrode.